Digital signal processors (DSP) are often connected to external FIFO memory at an expansion bus interface or external memory interface. The expansion bus interface uses direct memory access (DMA) to link the digital signal processor core and its peripheral devices to the expansion bus. Synchronous first-in-first-out (FIFO) devices with deep pipelines enable burst transfer of large amounts of data in the form of frames in rapid succession over many clock cycles. The term synchronous FIFO implies that the FIFO read or write accesses are synchronous to the read or write clock, respectively. Clocks are both locked in time to the system clock. The term synchronization event refers to an event, generated by the FIFO which causes the DSP/DMA controller to read (or write) a given or known amount of data. For this discussion, the synchronization event is closely related to the activation of a FIFO status flags. These FIFO status flags may include Almost Empty (PAE), Almost Full (PAF), Half Full (HF). These operations can be carried out only with full synchronism between the DSP and the FIFO.
FIG. 1 illustrates a pair of conventional synchronous FIFOs 101 and 102 connected to the expansion bus 100 of a conventional DSP. FIFO 101 permits the expansion bus to read in external data. FIFO 102 permits the expansion bus to write data out to external devices. The expansion bus 100 is normally only one of many peripheral interface devices connected to the direct memory access (DMA) within the DSP via a DMA control bus and a DNA data bus. The expansion bus clock XPCLK 103 is derived from DSP system clock and drives both the read clock of FIFO 101 and the write clock of FIFO 102. Data flows to the expansion bus port XD(N:0) 117 from FIFO 101 Q(N:0) output 105 via I/O path 104. Data flows to the D(N:0) input 106 of FIFO 102 from expansion bus port XD(N:0) 117 via I/O path 104. FIFO flags PAE 111 (almost empty flag) and PAF 112 (almost full flag) are two of the possible flags that may be used to signal the INTx 109 and INTy 110 expansion bus inputs is possible. Expansion bus enable signals 107 (XCEx, XOE, XOE and XOE) drive the enable logic 108 configured to control the FIFO enables as required. FIFO 101 inputs data on D(N:0) input 115 as timed by write clock 113. FIFO 102 output data on Q(N:0) output 116 as timed by read clock 114.
FIFOs 101 and 102 are typically used in one of three modes. In the first mode, the system reads from or writes to the FIFO at a fixed rate without regard for the FIFO flags. The inbound and outbound rates from a given FIFO are matched such that overflow or underflow does not normally occur. In the event that an overflow or underflow does occur there is generally a recovery mechanism provided by the system. In some cases there is no need for recovery mechanism because data loss is acceptable. In the second mode, the system is tightly coupled to the FIFO and is able to halt accesses to the FIFO based on the status of the empty flag for a read or the full flag for a write. In the third mode, a system is loosely coupled to the FIFO and performs a burst transfer based on the status of one of the intermediate flags. Among these flags are half full, almost full, or almost empty. The almost full and almost empty flags are typically user defined by the value stored in an offset register in programmable FIFOs. The length of the burst will typically match the offset defined by the given flag. This burst transfer mode of operation of mode 3 is of prime interest here.
Flag Triggered Burst Synchronization in DSPS Without Synchronization Control
Consider the case of a digital signal processor with read bursts triggered when the half full flag HF switches to an active high state. When the HF flag switches from low to high, the digital signal processor initiates a read burst from the FIFO of length HF, which is half the FIFO depth. In digital signal processors without frame synchronization control, having synchronization events triggered from programmable FIFO flags such as HF is likely to produce problematical conditions. There are two separate problem conditions for a read burst. A similar analysis shows that the counterpart of these two scenarios can occur for write bursts to the FIFO.
The first problem occurs as follows. Assume the FIFO is 1024 words deep and the HF Flag is set to become active at 512 words occupancy. Assume further that bursts are set to occur in 512 word increments. This means that a burst read by the digital signal processor from the FIFO is initiated when the FIFO HF Flag transitions to the active state and signals that the FIFO contains 512 or more words. In general, the read and write side for the FIFO do not have to both operate in the same use model as defined above. It will be typical for the digital signal processor side of the FIFO to operate in mode 3, while the other side operates in mode 1 or 2. A write burst into the FIFO from an external source is initiated when the HF Flag transitions to the inactive state signaling that the FIFO contains less than 512 words. If the write operation proceeds faster than the read operation, it is possible to have two sequential write bursts without having a full read burst between them. Without the full read burst in between these two write bursts, the FIFO then gets locked into a state where more than 512 words are stored and no read burst request initiated from the HF Flag can occur.
The second problem occurs as follows. Assume the FIFO is 1024 words deep and the HF Flag is inactive initially with the FIFO storing one less than 512 words occupancy. Assume again that bursts are set to occur in 512 word increments. In this scenario a burst read by the digital signal processor from the FIFO is initiated when the FIFO HF Flag transitions to the active state and signals that the FIFO contains 512 or more words. It also means that a write burst into the FIFO from an external source is initiated when the HF Flag transitions to the inactive state signaling that the FIFO contains less than 512 words. Combinations of alternating single word writes with single word reads can cause spurious events to be generated. This means that a succession of two burst reads by the DSP from the FIFO can be initiated without an intervening write burst and an underflow results.
These two scenarios indicate that triggering a synchronization event in the digital signal processor from a FIFO flag such as half full flag HF is subject to possible malfunction. In general the risk is incurred when bursts are interrupted before completion. Thus if the read burst is interleaved in time with a write burst in process, or conversely if the write burst is interleaved in time with a read burst in process, problems can arise. The normal practice to avoid this is to force the direct memory access unit to ignore events requesting service during a current frame transfer. For example, for a typical data transfer the beginning of which was synchronized by detecting an active. almost full flag PAF 112 during a DSP burst read from a FIFO, the FIFO resets the PAF flag 112 to the inactive high state after the first piece of data was read. If the PAF flag 112 were to stay inactive during the burst, this would indicate that the data source is permitted to write additional data to the FIFO before the direct memory access unit completes reading the burst frame.
In an example of a direct memory access unit controlled solution, after a frame is completed, the direct memory access unit waits an additional n-clock cycles before checking to determine if the flag is still active. This is merely to account for any synchronization delays within the FIFO between when an access occurs and when the flag is updated. If it is still active, the next frame will be synchronized based on the fact that the flag is still active. This delay is needed to give the external FIFO time to update its flags and give the PAF flag 112 time to propagate through the internal registers before being registered inside the direct memory access unit. For example, a FIFO typically takes approximately one to three FIFO clock cycles to update its PAF flag 112 externally.
In addition, the direct memory access unit must mask spurious transitions on the flag input while the transfer is in progress, and wait n-additional cycles before reevaluating the flag. The difficulties relating to generation of spurious transitions on the flag output is one that relates equally to the use of any of the available flags in a conventional FIFO.
FIG. 2 illustrates the timing relationships between a flag input to the digital signal processor, the generation of a direct memory access synchronization event, and the direct memory access frame. The EXT_INTl signal 201 is triggered, for example, by almost full signal PAF 112 or almost empty PAE signal 111 from a FIFO. (see 111 and 112 of FIG. 1). Further recognition of interrupts generating a DMA_Synch_Event signal 202 are ignored until the DMA_Frame 203 completes at time 205.
The transition of Flag_Input_to_EXT_INTl signal 201 from high to low while a burst is not in progress triggers direct memory access synchronizing event 202.
The negative edge of Flag_Input_to_EXT_INTl signal 201 triggers a frame transfer on signal DMA_Frame 203. This gates off DMA_Synch_Event signal at time 202. During the synchronization event, the transition on Flag_Input_to_EXT_INTl signal 201 at time 204 is ignored.
After a read burst completes internally at time 205, a delay of n-clock cycles 211 is inserted before another DAM_Synch_Event signal at time 206 checks whether Flag_Input_to_EXT_INTl signal 201 is active at time 207.
Because Flag_Input_to_EXT_INTl signal 201 is still active at time 207 after the burst and delay, the new DMA_Synch_Event at time 206 is registered inside the direct memory access unit.
The new direct memory access synchronization event triggers another DMA_Frame burst at time 208.
FIG. 3 illustrates a conventional FIFO device used in pairs (as in FIG. 1) for data transfer to and from the digital signal processor via the expansion bus. The FIFO includes RAM array 300 configured to accept data from WData input 301 via input register 302 and pass data to output register 303 and read output port 304. Synchronous read control logic 306 and write control logic 307 accept respective read clock 309 and write clock 310 from a common source at the expansion bus XFCLK clock output (103 in FIG. 1). Read pointer 313 and write pointer 314 collectively track the respective placements of read and write data handled by the FIFO. The pointers provide information for generation of flags and status in the status flag logic 316. A number of possible flags can be generated, such as: almost empty PAE flag 111; almost full PAF flag 112; and half full HF flag 118/119.